1. Field of the Invention
The present invention relates to a multiplex communication control apparatus which controls reception response (RSP) of multi-destination communication from one communication terminal to a plurality of communication terminals and of non-multi-destination communication from one communication terminal to another one in a multi communication system.
2. Description of the Related Art
FIG. 1 is a block diagram showing a configuration of a conventional multiplex communication control apparatus of each communication terminal in a multi communication system.
In FIG. 1, a portion surrounded by a broken line designates a multiplex communication control apparatus which is connected with a control microcomputer 30 and with a transmission line 50 through a bus transceiver 40. The configuration of the multiplex communication control apparatus is as follows.
Reference numeral 1 designates a microcomputer interface (I/F) which is connected with the control microcomputer 30 controlling the communication terminal and gives/receives data. The microcomputer interface 1 is controlled by a microcomputer interface control circuit 2 and gives/receives data between the multiplex communication control apparatus and the control microcomputer 30.
Reference numeral 3 designates a transmitting buffer for storing a transmitted data train which has been transferred from the control microcomputer 30 through the microcomputer interface 1 and is to be transmitted to another communication terminal. Reference numeral 4 designates a receiving buffer for storing a received data train which has been delivered from another communication terminal to this communication terminal through the transmission line 50. The transmitting buffer 3 and the receiving buffer 4 are controlled by a buffer control circuit 5 to store or read out the data train.
Reference numeral 6 designates a communication control circuit and this circuit 6 is connected with the transmission line 50 through a bus transceiver 40.
The communication control circuit 6 executes conversions of data trains in both of the buffers 3 and 4 and the communication data train at the transmission line 50. To be concrete, the communication control circuit 6 converts a parallel data train stored in the transmitting buffer 3 into communication frame which is to be delivered to the transmission line 50 and converts the communication frame at the transmission line 50 into a parallel data train so as to be stored in the receiving buffer 4. Transmission of data to another communication terminal and receiving of data from another communication terminal are controlled by CSMA/CD (Carrier Sense Multiple Access/Collision Detection) method.
Reference numeral 7 designates a self address register which stores a pre-determined peculiar address (self address) at each communication terminal, and a reception side terminal is appointed by the fact that the self address stored in the self address register 7 is transmitted as a control data in the communication frame.
Reference numeral 8 designates a multi-/non-multi-destination communication detection circuit which detects whether a transmission destination address (refer to FIG. 2) included in the control data in the communication frame received by the communication control circuit 6 is a multi-destination communication address (refer to FIG. 5(b)). The multi-destination communication is expressed by a lower priority (passive) signal train at the transmission line 50. The non-multi-destination communication, destined exclusively from one communication terminal to another one, is designating by a transmission destination address.
Reference numeral 9 designates a transmission error detection circuit as a supervision circuit which supervises whether or not anything abnormal happens in the transmitting state. The circuit 9 detects an error included in communication data which is transmitted to the transmission line 50 from the communication control circuit 6 at the transmitting time. Reference numeral 10 designates a reception error detection circuit as a supervision circuit which supervises whether or not anything abnormal happens in receiving state. The circuit 10 detects an error included in communication data which is transmitted to the transmission line 50 from the communication control circuit at the receiving time. Further, reference numeral 11 designates an overrun error detection circuit as a supervision circuit which supervises the state of the receiving buffer 4 at the receiving time, and the circuit 11 detects whether or not the receiving buffer 4 is in a full state at the receiving time.
Reference numeral 12 is an RSP control circuit which controls reception response (RSP) by an error signal and a multi-destination signal outputted from the aforesaid error detection circuits 10 and 11 and the multi-/non-multi-destination communication detection circuit 8 respectively. This RSP control circuit 12 gives an RSP transmission indication to an ACK register 13.
The ACK register 13 stores reception acknowledgment (ACK) data which sends it back to a transmission side terminal in the case where reception is completed normally.
The RSP control circuit 12 is composed of inverters 12a, 12b and 12c which input a multi-destination signal being an output signal from the multi-/non-multi-destination communication detection signal 8, output signals from the reception error detection circuit 10 and the overrun error detection circuit respectively, and a 3-input AND gate 12d which inputs the outputs from the respective inverters 12a, 12b and 12c. The output of the AND gate 12d is given to the ACK register 13.
FIG. 2(a) through FIG. 2(c) are schematic diagrams each showing configuration of data train (hereinafter frame) which is transmitted/received by a multi communication system.
As shown in FIG. 2(a), a transmission frame 100 is delivered from the transmission side terminal, the frame 100 being composed of identifier (SOM) 101 showing the start of transmission, a control data 102 including data indicating a transmission destination (transmission destination address), communication data 103 being communication content, identifier (EOD) 104 showing the end of communication data 103, and identifier (EOM) 105 showing the end of transmission from the transmission side terminal.
As shown in FIG. 2(b), at a reception side terminal, after identifier (EOD) 104 indicating end of transmission data of the transmission frame 100 is received by the reception side terminal, RSP 110 showing success or failure of reception is sent back therefrom. Since these data, that is, transmission frame 100 and RSP 110 are delivered to the same transmission line 50, communication is performed with a frame 120 having a configuration shown in FIG. 2(c).
Next, explanation will be given on the operation of a conventional multiplex communication control apparatus which is so configured as aforementioned and communicates data having such a frame configuration as aforementioned. In addition, FIG. 3(a) through FIG. 3(d) are schematic diagrams each showing a configuration of a communication frame of a conventional multiplex communication system.
The data train sent at the time of communication processing is transferred and stored in the transmitting buffer 3 from the control microcomputer 30 through the microcomputer interface 1 and microcomputer interface control circuit 2. When the transmit data is stored in the transmitting buffer 3, the buffer control circuit 5 transmits a transmit requesting signal to the communication control circuit 6. When the communication control circuit 6 receives the signal, it monitors the state of the transmission line 50 through the bus transceiver 40, and at that time, in the case where the transmission line 50 is detected to be in the state of non-communication (idle), it converts parallel data in the transmitting buffer 3 into serial data being from SOM 101 to EOD 104 of the communication frame 100 as shown in FIG. 2(a) so as to transmit it to the transmission line 50 and prepares to receive RSP from the reception side terminal.
The reception processing is performed in the aforesaid procedure, wherein serial communication data 120 having been delivered to the transmission line 50 from another communication terminal is detected by the communication control circuit 6 through the bus transceiver 40 serial data at the transmission line 50 is separated and detected according to communication frame and is converted into parallel data which can be stored in the receiving buffer 4. The communication control circuit 6 compares a transmission destination address included in control data 102 transmitted following identifier (SOM) 101 showing the start of transmission in communication frame 120 with a self address stored in the self address register 7 and judges whether or not communication frame 120 is destined for itself.
At the same time, the multi-/non-multi-destination communication detection circuit 8 judges whether or not a transmission destination address is a dedicated address (multi-destination address) for multi-destination communication received by all of the terminals other than a transmission side terminal. In the case where a transmission destination address is detected that it coincides either with a self address our with a multi-destination address, the transmission destination address is stored in the ACK register 13 as ACK data to be sent back at the time of normal reception as well as communication data 103 having been transmitted as communication frame 120 following the control data 102 which is converted into parallel data. At this time, the overrun error detection circuit 11 detects whether or not the receiving buffer 4 is already full of received data, and only in the case where the receiving buffer is confirmed to be empty, both of control data and communication data are stored in the receiving buffer 4 through the buffer control circuit 5.
In the case where the overrun error detection circuit 11 detects an overrun error of the receiving buffer 4 being in the full state, the buffer control circuit 5 prohibits receive data from being stored in the receiving buffer 4 and abandons this received data.
In the non-multi-destination communication, a transmission destination address and a self address coincide with each other. In the case where the reception error detection circuit 10, which detects whether or not an error state not satisfying a frame agreement and a bit agreement of data has occurred, does not detect an error, and the aforesaid overrun error detection circuit 11 does not detect an error in a reception period of a communication frame from SOM 101 to EOD 104 having been detected by the communication control circuit 6, the fact that a reception error and an overrun error did not occur is announced to the RSP control circuit 12 by a predetermined signal. When the RSP control circuit 12 receives the signal, after detecting EOD 104, it delivers transmission address data stored in advance in the ACK register 13 according to the aforesaid processing to the transmission line 50 as ACK data through the communication control circuit 6 and announces to the transmission side terminal that a normal transmission has been done (refer to FIG. 3(a)).
In the case where the fact that a reception error or an overrun error occurs is detected by the reception error detection circuit 10 or the overrun error detection circuit 11, the RSP control circuit 12 prohibits the data stored in the ACK register 13 from being delivered. It also announces to the transmission side terminal that an error has occurred at a reception side terminal by not delivering the RSP 110 to the transmission line 50 (refer to FIG. 3(b)).
The transmission side terminal detects RSP 110, which has been sent back from the reception side terminal after EOD 104 of the communication frame 120, by the transmission error detection circuit 9 through the communication control circuit 6, thereby confirming whether or not the sent back data is normally received at the reception side terminal. In the case where RSP 110 is not, sent, back, it announces to the buffer control circuit 5 that a transmission error occurred. The buffer control circuit 5 announces to the control microcomputer 30 the occurrence of the transmission error through the microcomputer interface control circuit 2. In answer to this, the control microcomputer 30 makes the transmission side terminal perform a transmission control such as re-sending.
In multi-destination communication in which a multi-destination address is designated as a transmission destination address, all of the communication terminals other than a transmission side terminal become the reception side terminals. In this case, when a reception error or an overrun error occurs at one reception side terminal, the terminal does not deliver RSP in the same way as the case of non-multi-destination communication. Therefore, when the fact that an error occurs is announced from the reception terminal to the transmission side terminal, in the case where ACK is delivered from other terminals at which a transmission has been received normally, the transmission frame 100 without RSP 110 which has lower priority at the transmission line 50 is not sent back. Therefore, RSP 110 is not delivered regardless of a presence of error occurrence (refer to FIG. (c), (d)). Therefore, also at the transmission side terminal, the transmission error detection circuit 9 does not detect an error concerning RSP 110. Accordingly, the error concerning RSP 110 is not announced to the control microcomputer 30 through the buffer control circuit 5.
By the way, the conventional multiplex communication control apparatus is so constructed as aforementioned RSP from a reception side terminal to a transmission side terminals does not exist at the time of multi-destination communication, and the fact whether or not all of a plurality of the reception side terminal received a transmission normally cannot confirmed at the transmission side terminal. Especially, in the case where an overrun error at the reception side terminal occurs, error effect does not appear at the transmission line. Therefore there is a problem that there are terminals at which a transmission has been received normally and terminals at which a transmission cannot have been received normally. Also at the time of non-multi-destination communication, the transmission side terminal cannot distinguish between a reception error from an overrun error, therefore there is a problem that the period of re-sending a transmission cannot be controlled.